1. Field of the Invention
The present invention relates to an apparatus and a method for establishing signal synchronization between transmission lines using the ITU-T-standardized SDH (Synchronous Digital Hierarchy) and the U.S. SONET (Synchronous Optical Network) transmission system, for example. The present invention relates particularly to an apparatus and a method for establishing signal synchronization between transmission lines, prior to switching the lines from a regular line to an alternative line without interrupted, lost or error data (hereinafter called uninterrupted line switching).
Conventionally, control and maintenance information was included in a higher-order-group signal and the line switching was performed at a level of a lower-order group signal. However, to improve the transmission quality of trunk transmission line, it is recently in great demand that the control and maintenance information is included in a higher-order-group signal and that the uninterrupted line switching is performed at a higher-order-group signal level.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional system for establishing signal synchronization between lines. FIG. 2 is a timing chart illustrating the conventional system for establishing signal synchronization between lines.
In FIG. 1, a regular line is connected from a station A directly to a station B; an alternative line is connected from the station A to the station B via a station C.
A sending terminal equipment of station A is comprised of a frame pulse (FP) inserter and a branch circuit. A transmission signal is separated in two by the branch circuit (BR CKT), which signals are transmitted respectively from station A to station B simultaneously over the regular and alternative lines (hereinafter the signals are called a regular-line signal and an alternative-line signal, respectively).
A receiving terminal equipment of station B is comprised of a controller and a selector; corresponding to the regular line (or on the regular side), a delay circuit (or memory having a fixed storage capacity) and a frame pulse (FP) detector; and corresponding to the alternative line (or on the alternative side), an elastic memory and a frame pulse detector.
Referring to FIG. 2, operations of the conventional signal synchronizing system are explained. In station A, the frame pulse inserter inserts in a transmission signal, a signal of a particular form (hereinafter the signal is called a frame pulse).
(1) The transmission signal including the frame pulse is separated in two by the branch circuit, which signals are transmitted from station A over the regular and alternative lines. PA1 (2) The transmission signal transmitted via the regular line (regular-line signal) reaches station B after a propagation delay DL1 of the regular line. PA1 (3) The transmission signal transmitted via the alternative line (alternative-line signal) reaches station B after a propagation delay DL2 of the alternative line, which is larger than DL1 because the signal passes through station C. PA1 (4) In station B, the delay circuit causes the regular-line signal to delay further than the alternative-line signal does. That is, the delay circuit causes a delay DL3 to the regular-line signal so that the regular-line signal is output from the delay circuit later than the alternative-line signal reaches station B.
The regular-line signal is output from the selector outside the station B via the delay circuit and FP detector provided for the regular line (i.e., on the regular side). The regular-side FP detector detects the frame pulse in the regular-line signal and outputs a detection signal to the controller.
On the other hand, a byte of the incoming alternative-line signal is sequentially stored in the elastic memory and when the memory is full, the signal is read therefrom bytewise in a FIFO fashion every time a byte of the signal is input to the memory. The storage capacity of the elastic memory can be specified dynamically in byte units by the controller. The signal read from the elastic memory is output to the selector through the FP detector. The alternative-side FP detector detects the frame pulse in the incoming signal to output a detection signal to the controller.
The controller determines whether the detection signals occur at the same time from the respective FP detectors. When the determination is negative, the controller delays the data output from the elastic memory by increasing the storage capacity of the elastic memory. The above operation is repeated until both FP detectors output the detection signals at the same time. When the determination is positive, the controller recognizes that the signals on both lines are synchronized. Therefore, the lines can be switched uninterruptedly from the regular to the alternative by controlling the selector so as to select the signal output from the alternative-side frame pulse detector.
As described above, the conventional system delayed the regular-line signal later than the alternative-line signal by previously providing the delay circuit to the regular side, eventually causing an excess delay to the regular-line signal even in the usual operation. To make matters worse, the alternative-line signal is delayed further than the regular-line signal when the lines are switched to the alternative.
Therefore, a problem is that a communication network including stations having such delay is not preferable since the delay is added each time a signal passes through a station, causing undue delay in the entire network.